1. Field of the Invention
The present invention relates to the field of semiconductor packaging, and, more particularly, to a 3-D semiconductor device and semiconductor process for manufacturing the same.
2. Description of the Related Art
In stacked-chip packaging, multiple integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This increases stack density, making the package structure smaller, and often reduces the length of the path that signals must traverse between chips. Thus, stacked-chip packaging tends to increase the speed of signal transmission between or among chips. Additionally, stacked-chip packaging allows chips having different functions to be integrated in a single package structure. Use of through silicon vias (TSV) has been a key technology in realizing stacked-chip packaging integration due to the ability to provide short vertical conductive paths between chips.